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Data Sheet
ADE7880
Parameter 1 , 2
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
PSM0 Mode
For specified performance
VDD Pin
2.97
3.63
V
Minimum = 3.3 V ? 10%; maximum =
3.3 V + 10%
I DD
25
28
mA
PSM1 and PSM2 Modes
VDD Pin
2.4
3.7
V
I DD
PSM1 Mode
PSM2 Mode
PSM3 Mode
VDD Pin
I DD in PSM3 Mode
2.4
5.3
0.2
1.8
5.8
0.27
3.7
6
mA
mA
V
μA
For specified performance
1
2
3
4
See the Typical Performance Characteristics section.
See the Terminology section for a definition of the parameters.
? 2800 ?
? ? means the whole number of the division.
? f L ?
The CLKIN/CLKOUT load capacitors refer to the capacitors that are mounted between the CLKIN and CLKOUT pins of the ADE7880 and AGND. The capacitors should
be chosen based on the crystal manufacturer’s data sheet specification, and they must not have more than the maximum value specified in the table.
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T MIN to T MAX = ?40°C to +85°C. Note that dual
function pin names are referenced by the relevant function only within the timing tables and diagrams (see the Pin Configuration and
Function Descriptions section for full pin mnemonics and descriptions).
Table 2. I 2 C-Compatible Interface Timing Parameter
Standard Mode
Fast Mode
Parameter
SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of SCL Clock
High Period of SCL Clock
Set-Up Time for Repeated Start Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Symbol
f SCL
t HD;STA
t LOW
t HIGH
t SU;STA
t HD;DAT
t SU;DAT
t R
t F
Min
0
4.0
4.7
4.0
4.7
0
250
Max
100
3.45
1000
300
Min
0
0.6
1.3
0.6
0.6
0
100
20
20
Max
400
0.9
300
300
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Suppressed Spikes
t SU;STO
t BUF
t SP
4.0
4.7
N/A 1
0.6
1.3
50
μs
μs
ns
1
N/A means not applicable.
Rev. A | Page 7 of 104
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